The design of large scale integrated circuit by the assembly of functional blocks, logic synthesis, is to a considerable extent now done by computers. Logic synthesis which is a part of computer-aided-design (CAD) largely involves the assembly of logic gates and memory latches to achieve a specific function. While logic synthesis is usually able to deliver area-efficient testable designs, the performance of designs synthesized by simple assembly of logic gates and latches remains a major concern.
For this reason, it is now usual practice to include special provisions for optimizing the basic design. Hitherto, most of the optimization work has been concentrated on combinational circuits, which are circuits consisting solely of logic gates without memory elements such as latches. However, most practical designs are sequential in nature and include memory elements such as latches, and so sequential circuits have also attracted attention for optimization.
One approach to optimization of sequential circuits has been simply to optimize the combinational logic blocks between the latches. However, this approach has limited possibilities, since it does not exploit the sequential nature of the circuit.
Another approach to optimization, or shortening, of the clock period of synchronous sequential circuits involves retiming in which only the sequential elements are considered, the combinational logic being assumed to be fixed. Retiming basically involves the repositioning of latches in the circuit to shorten the path length between selected latches and thereby shorten the path of the affected combinational subcircuits.
However, in the past these and basically similar techniques have not fully exploited the characteristics of sequential synchronous circuits and so have not always achieved the optimum results possible.
An object of this invention is to make retiming techniques more effective to speed up VLSI circuits that include synchronous sequential circuits.